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cy2308 3.3v zero delay buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07146 rev. *e revised august 03, 2007 features zero input-output propagation delay, adjustable by capacitive load on fbk input multiple configurations, see ?available cy2308 configura- tions? on page 3 multiple low skew outputs two banks of four outputs, three-stateable by two select inputs 10 mhz to 133 mhz operating range 75 ps typical cycle-to-cycle jitter (15 pf, 66 mhz) space saving 16-pin 150 mil soic package or 16-pin tssop 3.3v operation industrial temperature available functional description the cy2308 is a 3.3v zero delay buffer designed to distribute high speed clocks in pc, workst ation, datacom, telecom, and other high performance applications. the part has an on-chip pll t hat locks to an input clock presented on the ref pin. the pl l feedback is driven into the fbk pin and obtained from one of the outputs. the input-to-output skew is less than 350 ps and output-to-output skew is less than 200 ps. the cy2308 has two banks of four outputs each that is controlled by the select inputs as shown in the table ?select input decoding? on page 2 ?. if all output clocks are not required, bank b is three-stated. the input clock is directly applied to the output for chip and system testing purposes by the select inputs. the cy2308 pll enters a power down state when there are no rising edges on the ref input. in this mode, all outputs are three-stated and the pll is turned off resulting in less than 50 a of current draw. the pll shuts down in two additional cases as shown in the table ?select input decoding? on page 2. multiple cy2308 devices accept the same input clock and distribute it in a system. in th is case, the skew between the outputs of two devices is less than 700 ps. the cy2308 is available in five different configurations as shown in the table ?available cy2308 configurations? on page 3. the cy2308?1 is the base part where the output frequencies equal the reference if there is no counter in the feedback path. the cy2308?1h is the high drive version of the ?1 and rise and fall times on this device are much faster. the cy2308?2 enables the user to obtain 2x and 1x frequencies on each output bank. the exact configuration and output frequencies depend on the output that drives the feedback pin. the cy2308?3 enables the user to obtain 4x and 2x frequencies on the outputs. the cy2308?4 enables the user to obtain 2x clocks on all outputs. thus, the part is extrem ely versatile and is used in a variety of applications. the cy2308?5h is a high drive version with ref/2 on both banks. ref clka1 clka2 clka3 clka4 fbk pll mux select input decoding s2 s1 clkb1 clkb2 clkb3 clkb4 /2 extra divider (?2, ?3) /2 extra divider (?3, ?4) extra divider (?5h) /2 logic block diagram [+] feedback
cy2308 document number: 38-07146 rev. *e page 2 of 15 pinouts figure 1. pin diagram - 16 pin soic table 1. pin defini tions - 16 pin soic pin signal description 1ref [1] input reference frequency, 5v tolerant input 2 clka1 [2] clock output, bank a 3 clka2 [2] clock output, bank a 4v dd 3.3v supply 5 gnd ground 6 clkb1 [2] clock output, bank b 7 clkb2 [2] clock output, bank b 8s2 [3] select input, bit 2 9s1 [3] select input, bit 1 10 clkb3 [2] clock output, bank b 11 clkb4 [2] clock output, bank b 12 gnd ground 13 v dd 3.3v supply 14 clka3 [2] clock output, bank a 15 clka4 [2] clock output, bank a 16 fbk pll feedback input 9 16 fbk clka4 clka3 v dd gnd clkb4 clkb3 s1 1 2 3 4 5 6 7 8 10 11 12 13 14 15 ref clka1 clka2 v dd gnd clkb1 clkb2 s2 top view select input decoding s2 s1 clock a1?a4 clock b1?b4 output source pll shutdown 0 0 tri-state tri-state pll y 0 1 driven tri-state pll n 1 0 driven [4] driven [4] reference y 1 1 driven driven pll n notes 1. weak pull down. 2. weak pull down on all outputs. 3. weak pull ups on these inputs. 4. outputs inverted on 2308?2 and 2308?3 in bypass mode, s2 = 1 and s1 = 0. [+] feedback
cy2308 document number: 38-07146 rev. *e page 3 of 15 zero delay and skew control to close the feedback loop of t he cy2308, the fbk pin is driven from any of the eight available ou tput pins. the output driving the fbk pin drives a total load of 7 pf plus any additional load that it drives. the relative loading of this output to the remaining outputs adjusts the input-output delay. this is shown in the ta b l e 2 . for applications requiring zero input-output delay, all outputs including the one providing feedback is equally loaded. if input-output delay adjustm ents are required, use the zero delay and skew control graph to calculate loading differences between the feedback output and remaining outputs. for zero output-output skew, outputs are loaded equally. for further information on using cy2308, refer to the application note ?cy2308: zero delay buffer.? available cy2308 configurations device feedback from bank a frequency bank b frequency cy2308?1 bank a or bank b reference reference cy2308?1h bank a or bank b reference reference cy2308?2 bank a reference reference/2 cy2308?2 bank b 2 x reference reference cy2308?3 bank a 2 x reference reference or reference [5] cy2308?3 bank b 4 x reference 2 x reference cy2308?4 bank a or bank b 2 x reference 2 x reference cy2308?5h bank a or bank b reference /2 reference /2 table 2. ref. input to clka/clkb delay versus difference in lo ading between fbk pin and clka/clkb pins note 5. output phase is indeterminant (0 or 180 from input clock). if phase integrity is required, use the cy2308?2. [+] feedback
cy2308 document number: 38-07146 rev. *e page 4 of 15 maximum ratings supply voltage to ground potentia l................?0.5v to +7.0v dc input voltage (except ref) .............. ?0.5v to v dd + 0.5v dc input voltage ref ........................................... ?0.5 to 7v storage temperature .................................. ?65c to +150c junction temperature .................................................. 150c static discharge voltage (mil-std-883, method 3015)..... .............. .............. ... >2000v operating conditions for co mmercial temperature devices parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (amb ient temperature) 0 70 c c l load capacitance, below 100 mhz ? 30 pf load capacitance, from 100 mhz to 133 mhz ? 15 pf c in input capacitance [6] ?7pf t pu power up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms electrical characteristics for commercial temperature devices parameter description test conditions min max unit v il input low voltage ? 0.8 v v ih input high voltage 2.0 ? v i il input low current v in = 0v ? 50.0 a i ih input high current v in = v dd ? 100.0 a v ol output low voltage [7] i ol = 8 ma (?1, ?2, ?3, ?4) i ol = 12 ma (?1h, ?5h) ?0.4v v oh output high voltage [7] i oh = ?8 ma (?1, ?2, ?3, ?4) i oh = ?12 ma (?1h, ?5h) 2.4 ? v i dd (pd mode) power down supply current ref = 0 mhz ? 12.0 a i dd supply current unloaded outputs, 100 mhz ref, select inputs at v dd or gnd ?45.0ma ? 70.0 (?1h,?5h) ma unloaded outputs, 66 mhz ref (?1, ?2, ?3, ?4) ?32.0ma unloaded outputs, 33 mhz ref (?1, ?2, ?3, ?4) ?18.0ma note 6. applies to both ref clock and fbk. 7. parameter is guaranteed by design and char acterization. not 100% tested in production. [+] feedback
cy2308 document number: 38-07146 rev. *e page 5 of 15 switching characteristics for commercial temperature devices [8] parameter name test conditions min. typ. max. unit t 1 output frequency 30-pf load, all devices 10 ? 100 mhz t 1 output frequency 20-pf load, ?1h, ?5h devices [9] 10 ? 133.3 mhz t 1 output frequency 15-pf load, ?1 , ?2, ?3, ?4 devices 10 ? 133.3 mhz duty cycle [7] = t 2 t 1 (?1, ?2, ?3, ?4, ?1h, ?5h) measured at 1.4v, f out = 66.66 mhz 30-pf load 40.0 50.0 60.0 % duty cycle [7] = t 2 t 1 (?1, ?2, ?3, ?4, ?1h, ?5h) measured at 1.4v, f out <50.0 mhz 15-pf load 45.0 50.0 55.0 % t 3 rise time [7] (?1, ?2, ?3, ?4) measured between 0.8v and 2.0v, 30-pf load ? ? 2.20 ns t 3 rise time [7] (?1, ?2, ?3, ?4) measured between 0.8v and 2.0v, 15-pf load ? ? 1.50 ns t 3 rise time [7] (?1h, ?5h) measured between 0.8v and 2.0v, 30-pf load ? ? 1.50 ns t 4 fall time [7] (?1, ?2, ?3, ?4) measured between 0.8v and 2.0v, 30-pf load ? ? 2.20 ns t 4 fall time [7] (?1, ?2, ?3, ?4) measured between 0.8v and 2.0v, 15-pf load ? ? 1.50 ns t 4 fall time [7] (?1h, ?5h) measured between 0.8v and 2.0v, 30-pf load ? ? 1.25 ns t 5 output to output skew on same bank (?1, ?2, ?3, ?4) [7] all outputs equally loaded ? ? 200 ps output to output skew (?1h, ?5h) all outputs equally loaded ? ? 200 ps output bank a to output bank b skew (?1, ?4, ?5h) all outputs equally loaded ? ? 200 ps output bank a to output bank b skew (?2, ?3) all outputs equally loaded ? ? 400 ps t 6 delay, ref rising edge to fbk rising edge [7] measured at v dd /2 ? 0 250 ps t 7 device to device skew [7] measured at v dd /2 on the fbk pins of devices ?0700ps t 8 output slew rate [7] measured between 0.8v and 2.0v on ?1h, ?5h device using test circuit 2 1? v/ns t j cycle to cycle jitter [7] (?1, ?1h, ?4, ?5h) measured at 66.67 mhz, loaded outputs, 15-pf load ?75200ps measured at 66.67 mhz, loaded outputs, 30-pf load ??200ps measured at 133.3 mhz, loaded outputs, 15-pf load ??100ps t j cycle to cycle jitter [7] (?2, ?3) measured at 66.67 mhz, loaded outputs 30-pf load ??400ps measured at 66.67 mhz, loaded outputs 15-pf load ??400ps t lock pll lock time [7] stable power supply, valid clocks presented on ref and fbk pins ??1.0ms notes 8. all parameters are specified with loaded outputs. 9. cy2308?5h has maximum input frequency of 133.33 mhz and maximum output of 66.67 mhz. [+] feedback
cy2308 document number: 38-07146 rev. *e page 6 of 15 operating conditions for i ndustrial temper ature devices parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (amb ient temperature) ?40 85 c c l load capacitance, below 100 mhz ? 30 pf load capacitance, from 100 mhz to 133 mhz ? 15 pf c in input capacitance [6] ?7pf t pu power-up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms electrical characteristics for in dustrial temperature devices parameter description test conditions min max unit v il input low voltage ? 0.8 v v ih input high voltage 2.0 ? v i il input low current v in = 0v ? 50.0 a i ih input high current v in = v dd ? 100.0 a v ol output low voltage [7] i ol = 8 ma (?1, ?2, ?3, ?4) i ol = 12 ma (?1h, ?5h) ?0.4v v oh output high voltage [7] i oh = ?8 ma (?1, ?2, ?3, ?4) i oh = ?12 ma (?1h, ?5h) 2.4 ? v i dd (pd mode) power down supply current ref = 0 mhz ? 25.0 a i dd supply current unloaded outputs, 100 mhz, select inputs at v dd or gnd ?45.0ma ? 70(?1h,?5h) ma unloaded outputs, 66 mhz ref (?1, ?2, ?3, ?4) ?35.0ma unloaded outputs, 66 mhz ref (?1, ?2, ?3, ?4) ?20.0ma [+] feedback
cy2308 document number: 38-07146 rev. *e page 7 of 15 switching characteristics for industrial temperature devices [8] parameter name test conditions min typ max unit t 1 output frequency 30 pf load, all devices 10 ? 100 mhz t 1 output frequency 20 pf load, ?1h, ?5h devices [9] 10 ? 133.3 mhz t 1 output frequency 15 pf load, ?1, ?2, ?3, ?4 devices 10 ? 133.3 mhz duty cycle [7] = t 2 t 1 (?1, ?2, ?3, ?4, ?1h, ?5h) measured at 1.4v, f out = 66.66 mhz 30 pf load 40.0 50.0 60.0 % duty cycle [7] = t 2 t 1 (?1, ?2, ?3, ?4, ?1h, ?5h) measured at 1.4v, f out <50.0 mhz 15 pf load 45.0 50.0 55.0 % t 3 rise time [7] (?1, ?2, ?3, ?4) measured between 0.8v and 2.0v, 30 pf load ? ? 2.50 ns t 3 rise time [7] (?1, ?2, ?3, ?4) measured between 0.8v and 2.0v, 15 pf load ? ? 1.50 ns t 3 rise time [7] (?1h, ?5h) measured between 0.8v and 2.0v, 30 pf load ? ? 1.50 ns t 4 fall time [7] (?1, ?2, ?3, ?4) measured between 0.8v and 2.0v, 30 pf load ? ? 2.50 ns t 4 fall time [7] (?1, ?2, ?3, ?4) measured between 0.8v and 2.0v, 15 pf load ? ? 1.50 ns t 4 fall time [7] (?1h, ?5h) measured between 0.8v and 2.0v, 30 pf load ? ? 1.25 ns t 5 output to output skew on same bank (?1, ?2, ?3, ?4) [7] all outputs equally loaded ? ? 200 ps output to output skew (?1h, ?5h) all outputs equally loaded ? ? 200 ps output bank a to output bank b skew (?1, ?4, ?5h) all outputs equally loaded ? ? 200 ps output bank a to output bank b skew (?2, ?3) all outputs equally loaded ? ? 400 ps t 6 delay, ref rising edge to fbk rising edge [7] measured at v dd /2 ? 0 250 ps t 7 device to device skew [7] measured at v dd /2 on the fbk pins of devices ? 0 700 ps t 8 output slew rate [7] measured between 0.8v and 2.0v on ?1h, ?5h device using test circuit 2 1? ?v/ns t j cycle to cycle jitter [7] (?1, ?1h, ?4, ?5h) measured at 66.67 mhz, loaded outputs, 15 pf load ? 75 200 ps measured at 66.67 mhz, loaded outputs, 30 pf load ? ? 200 ps measured at 133.3 mhz, loaded outputs, 15 pf load ? ? 100 ps t j cycle to cycle jitter [7] (?2, ?3) measured at 66.67 mhz, loaded outputs 30 pf load ? ? 400 ps measured at 66.67 mhz, loaded outputs 15 pf load ? ? 400 ps t lock pll lock time [7] stable power supply, valid clocks presented on ref and fbk pins ??1.0ms [+] feedback
cy2308 document number: 38-07146 rev. *e page 8 of 15 switching waveforms t 1 t 2 1.4v 1.4v 1.4v figure 2. duty cycle timing output t 3 3.3v 0v 0.8v 2.0v 2.0v 0.8v t 4 figure 3. all outputs rise/fall time 1.4v t 5 output output 1.4v figure 4. output-output skew v dd /2 t 6 input fbk v dd /2 figure 5. input-output propagation delay v dd /2 v dd /2 t 7 fbk, device 1 fbk, device 2 figure 6. device-device skew [+] feedback
cy2308 document number: 38-07146 rev. *e page 9 of 15 typical duty cycle [10] and i dd trends [11] for cy2308?1,2,3,4 notes 10. duty cycle is taken from typical chip measured at 1.4v. 11. i dd data is calculated from i dd = i core + ncvf, where i core is the unloaded current. (n = number of outputs; c = capacitance load per output (f); v = voltage supply (v); f = frequency (hz). duty cycle vs vdd (for 30 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.13.23.33.43.53.6 vdd (v) duty cycle (%) 33 mhz 66 mhz 100 mhz dut y cycle vs vdd (for 15 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (%) 33 mhz 66 mhz 100 mhz 133 mhz duty cycle vs frequency (for 30 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c duty cycle vs frequency (for 15 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c idd vs number of loaded outputs (for 30 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 10 0 12 0 14 0 02 468 number of loaded output s 33 m hz 66 m hz 100 m hz idd vs number of loaded outputs (for 15 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 10 0 12 0 14 0 02468 number of loaded output s 33 m hz 66 m hz 100 m hz [+] feedback
cy2308 document number: 38-07146 rev. *e page 10 of 15 typical duty cycle [10] and i dd trends [11] for cy2308?1h, 5h duty cycle vs vdd (for 30 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (% ) 33 mhz 66 mhz 100 mhz dut y cycle vs vdd (for 15 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (%) 33 mhz 66 mhz 100 mhz 133 mhz duty cycle vs frequency (for 30 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c dut y cycle vs vdd (for 15 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (%) 33 mhz 66 mhz 100 mhz 133 mhz duty cycle vs frequency (for 15 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c idd vs number of loaded outputs (for 30 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 10 0 12 0 14 0 02 468 number of loaded out put s 33 mhz 66 mhz 100 mhz idd vs number of loaded outputs (for 15 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 10 0 12 0 14 0 02468 number of loaded outputs 33 mhz 66 mhz 100 mhz [+] feedback
cy2308 document number: 38-07146 rev. *e page 11 of 15 test circuits 0.1 f v dd 0.1 f v dd clk out c load outputs gnd gnd test circuit 1 v dd 0.1 f v dd clk out 10 pf outputs gnd gnd 1 k 1 k 0.1 f test circuit for t 8 , output slew rate on ?1h, ?5 device test circuit for all parameters except t 8 test circuit 2 [+] feedback
cy2308 document number: 38-07146 rev. *e page 12 of 15 ordering information ordering code package type operating range cy2308sc?1 16-pin 150 mil soic commercial cy2308sc?1t 16-pin 150 mil soic - tape and reel commercial cy2308si?1 16-pin 150 mil soic industrial cy2308si?1t 16-pin 150 mil soic - tape and reel industrial cy2308sc?1h 16-pin 150 mil soic commercial cy2308sc?1ht 16-pin 150 mil soic - tape and reel commercial cy2308si?1h 16-pin 150 mil soic industrial cy2308si?1ht 16-pin 150 mil soic - tape and reel industrial cy2308zc?1h 16-pin 150 mil tssop commercial cy2308zc?1ht 16-pin 150 mil tssop - tape and reel commercial cy2308zi?1h 16-pin 150 mil tssop industrial cy2308zi?1ht 16-pin 150 mil tssop - tape and reel industrial cy2308sc?2 16-pin 150 mil soic commercial cy2308sc?2t 16-pin 150 mil soic - tape and reel commercial cy2308si?2 16-pin 150 mil soic industrial cy2308si?2t 16-pin 150 mil soic - tape and reel industrial cy2308sc?3 16-pin 150 mil soic commercial cy2308sc?3t 16-pin 150 mil soic - tape and reel commercial cy2308sc?4 16-pin 150 mil soic commercial cy2308sc?4t 16-pin 150 mil soic - tape and reel commercial cy2308si?4 16-pin 150 mil soic industrial cy2308si?4t 16-pin 150 mil soic - tape and reel industrial cy2308sc?5ht 16-pin 150 mil soic - tape and reel commercial pb-free cy2308sxc?1 16-pin 150 mil soic commercial cy2308sxc?1t 16-pin 150 mil soic - tape and reel commercial cy2308sxi?1 16-pin 150 mil soic industrial cy2308sxi?1t 16-pin 150 mil soic - tape and reel industrial cy2308sxc?1h 16-pin 150 mil soic commercial cy2308sxc?1ht 16-pin 150 mil soic - tape and reel commercial cy2308sxi?1h 16-pin 150 mil soic industrial cy2308sxi?1ht 16-pin 150 mil soic - tape and reel industrial cy2308zxc?1h 16-pin 150 mil tssop commercial cy2308zxc?1ht 16-pin 150 mil tssop - tape and reel commercial cy2308zxi?1h 16-pin 150 mil tssop industrial cy2308zxi?1ht 16-pin 150 mil tssop - tape and reel industrial cy2308sxc?2 16-pin 150 mil soic commercial cy2308sxc?2t 16-pin 150 mil soic - tape and reel commercial cy2308sxi?2 16-pin 150 mil soic industrial cy2308sxi?2t 16-pin 150 mil soic - tape and reel industrial cy2308sxc?3 16-pin 150 mil soic commercial cy2308sxc?3t 16-pin 150 mil soic - tape and reel commercial [+] feedback
cy2308 document number: 38-07146 rev. *e page 13 of 15 cy2308sxi?3 16-pin 150 mil soic industrial cy2308sxi?3t 16-pin 150 mil soic -tape and reel industrial cy2308sxc?4 16-pin 150 mil soic commercial cy2308sxc?4t 16-pin 150 mil soic - tape and reel commercial cy2308sxi?4 16-pin 150 mil soic industrial cy2308sxi?4t 16-pin 150 mil soic - tape and reel industrial cy2308sxc?5h 16-pin 150 mil soic commercial cy2308sxc?5ht 16-pin 150 mil soic - tape and reel commercial cy2308sxi?5h 16-pin 150 mil soic industrial cy2308sxi?5ht 16-pin 150 mil soic - tape and reel industrial ordering information (continued) ordering code package type operating range [+] feedback
cy2308 document number: 38-07146 rev. *e page 14 of 15 package drawings and dimensions pin 1 id 0~8 16 lead (150 mil) soic 1 8 916 seating plane 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.386[9.804] 0.393[9.982] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] dimensions in inches[mm] min. max. 0.016[0.406] 0.010[0.254] x 45 0.004[0.102] reference jedec ms-012 part # s16.15 standard pkg. sz16.15 lead free pkg. package weight 0.15gms 16-pin (150 mil) soic s16.15 51-85068-*b 4.90[0.193] 1.10[0.043] max. 0.65[0.025] 0.20[0.008] 0.05[0.002] 16 pin1id 6.50[0.256] seating plane 1 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] bsc. 5.10[0.200] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] bsc 0.25[0.010] 0-8 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] plane gauge dimensions in mm[inches] min. max. reference jedec mo-153 package weight 0.05 gms part # z16.173 standard pkg. zz16.173 lead free pkg. 16-pitssop4.40mmbdz16.173 51-85091-*a [+] feedback
document number: 38-07146 rev. *e revised august 03, 2007 page 15 of 15 psoc designer?, programmable system-on-chip ?, and psoc express? are trademarks and psoc? is a registered trademark of cypress s emiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i 2 c components from cypress or one of its sublicense d associated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. all products and company names mentioned in this document may be the trademarks of their respective holders. cy2308 ? cypress semiconductor corporation, 2007. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page document title: cy2308 3.3v zero delay buffer document number: 38-07146 rev. ecn no. issue date orig. of change description of change ** 110255 12/17/01 szv changed from spec ification number: 38-00528 to 38-07146 *a 118722 10/31/02 rgl added note 1 in page 2. *b 121832 12/14/02 rbi power up requirements added to operating conditions information *c 235854 see ecn rgl added pb-free devices *d 310594 see ecn rgl removed obsolete parts in the ordering information table specified typical value for cycle-to-cycle jitter *e 1344343 see ecn kvm/ved brought the ordering information table up to date: removed three obsolete parts and added two parts changed titles to tables that are specific to commercial and in dustrial temperature ranges [+] feedback

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